1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to the selective etching of a material comprising silicon nitride.
2. Description of the Related Art
Integrated circuits typically comprise a large number of circuit elements, which include, in particular, field effect transistors. In a field effect transistor, a gate electrode can be separated from a channel region by a gate insulation layer that provides an electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region are formed.
The channel region, the source region and the drain region can be formed in a semiconductor material, wherein the doping of the channel region is inverse to the doping of the source region and the drain region. Thus, there is a PN transition between the source region and the channel region, and between the channel region and the drain region. Depending on an electric voltage applied to the gate electrode, the field effect transistor can be switched between an on-state, wherein there is a relatively high electrical conductance between the source region and the drain region, and an off-state, wherein there is a relatively low electrical conductance between the source region and the drain region.
FIG. 1a shows a schematic cross-sectional view of a semiconductor structure 100 comprising a field effect transistor 102 in a first stage of a method of manufacturing the field effect transistor 102.
The semiconductor structure 100 comprises a substrate 101, and a semiconductor layer 103 formed on the substrate 101. The field effect transistor 102 further comprises a source region 104 and a drain region 105 that are formed in the semiconductor layer 103, and a gate electrode 108 that is separated from the semiconductor layer 103 by a gate insulation layer 107. A portion of the semiconductor layer 103 between the source region 104 and the drain region 105 and below the gate electrode 108 forms a channel region of the field effect transistor 102.
The source region 104, the drain region 105 and the gate electrode 108 may comprise silicide portions 120, 121 and 110, respectively. Adjacent the gate electrode 108, a silicon dioxide sidewall spacer 112 and a silicon nitride sidewall spacer 114 may be provided. A first liner layer 111 may be formed between the silicon dioxide sidewall spacer 112 and the gate electrode 108, and a second liner layer 113 may be formed between the silicon nitride sidewall spacer 114 and the silicon dioxide sidewall spacer 112. The first liner layer 111 may comprise silicon nitride, and the second liner layer 113 may comprise silicon dioxide.
The semiconductor structure 100 as shown in FIG. 1a may be formed by means of known manufacturing processes which may, in particular, include ion implantation processes for introducing dopant materials into the semiconductor layer 103, the source region 104 and the drain region 105, so that the doping of the source region 104 and the drain region 105 is inverse to the doping of the channel region. Absorption of ions by the silicon dioxide sidewall spacer 112 and/or the silicon nitride sidewall spacer 114 may be used for providing desired dopant profiles in the source region 104 and the drain region 105.
The silicide portions 120, 121, 110 in the source region 104, the drain region 105 and the gate electrode 108 may improve the electrical conductivities of the source region 104, the drain region 105 and the gate electrode 108, respectively. The silicide portions 120, 121, 110 may be formed by depositing a metal layer over the semiconductor structure 100 and initiating a chemical reaction between the metal and the semiconductor material in the layer 103 and the gate electrode 108, for example, by thermal activation.
After the formation of the source region 104, the drain region 105 and the silicide portions 120, 121, 110, a reactive ion etch (RIE) process may be performed for selectively removing a portion of the silicon nitride sidewall spacer 114, as shown schematically in FIG. 1a by arrows 122.
Reactive ion etching is a dry etch process, wherein ions and radicals are provided by an electric glow discharge that is created in a reactant gas. On the surface of the semiconductor structure 100, chemical reactions between materials of the semiconductor structure 100 and the ions and/or radicals may occur. Additionally, the surface of the semiconductor structure 100 may be bombarded with energetic ions, which may cause a sputtering of the surface. Due to the chemical reactions, and due to the sputtering, material may be removed from the surface of the semiconductor structure 100.
A selectivity of the reactive ion etch process 122 may be obtained by an appropriate selection of the reactant gas, and by an adaptation of parameters such as the pressure of the reactant gas and the power of the electric discharge. For selectively removing the silicon nitride sidewall spacer 114, the reactive ion etch process 122 may be adapted such that the silicon nitride of the silicon nitride sidewall spacer 114 is removed at a greater etch rate than other materials of the semiconductor structure 100. Thus, in the reactive ion etch process 122, the size of the silicon nitride sidewall spacer 114 may be reduced, as shown in FIG. 1b. 
FIG. 1b shows a schematic cross-sectional view of the semiconductor structure 100 in a later stage of the manufacturing process.
After the reactive ion etch process 122, a stressed dielectric layer 116 may be formed over the semiconductor structure 100. The stressed dielectric layer 116 may comprise silicon nitride and may have a tensile stress. An etch stop liner 115, which may comprise silicon dioxide, may be formed below the stressed dielectric layer 116.
The stressed dielectric layer 116 having a tensile stress may improve the mobility of electrons in the channel region of the field effect transistor 102, which may be particularly helpful if the field effect transistor 102 is an N-channel transistor. The stressed dielectric layer 116 may be removed from P-channel transistors in the semiconductor structure 100 by processes comprising lithography and etching, and a stressed dielectric layer having a compressive stress (not shown) may be formed over the P-channel transistors for improving the mobility of holes in the channel regions of the P-channel transistors.
By removing a part of the silicon nitride sidewall spacer 114 before forming the stressed dielectric layer 116, the pitch between the sidewall spacers of adjacent field effect transistors in the semiconductor structure 100 can be enlarged. This allows the creation of a thicker stressed dielectric layer 116, while avoiding the formation of voids in the stressed dielectric layer 116. Such voids might be filled with an electrically conductive material, such as tungsten, when electric contacts of the field effect transistor 102 are formed, leading to electrical shorts. A thicker stressed dielectric layer 116 can create a higher stress in the channel region of the field effect transistor 102. Moreover, by removing a part of the silicon nitride sidewall spacer 114, the stressed dielectric layer 116 can be provided at a smaller distance to the channel region. This may also be helpful for providing a higher stress in the channel region.
However, etching the silicon nitride sidewall spacer 114 by means of a reactive ion etch process as described above can have specific issues associated therewith, which will be explained in the following.
Depending on the techniques employed for forming the transistor 102 as shown in FIG. 1a, the silicon nitride sidewall spacer 114 may have small overhangs 119, wherein the silicon nitride sidewall spacer 114 extends to a slightly greater distance from the gate electrode 108 than the second liner layer 113, as shown in FIG. 1a. Below the overhangs 119, portions of the semiconductor material of the semiconductor layer 103 may be exposed adjacent the silicide portions 120, 121. Since typical reactive ion etch processes employed for the etching of silicon nitride are not selective to semiconductor materials such as silicon, pits 118, as shown in FIG. 1b, may be formed at locations where the material of the semiconductor layer 103 is exposed. The pits 118 may increase the electrical resistance between the silicide portions 120, 121 and the channel region of the transistor 102, which can adversely affect the performance of the transistor 102.
Moreover, during the reactive ion etch process 122, sputtering of the silicide in the silicide portions 120, 121, 110 may occur, so that the silicide gets slightly attacked and degraded, and metal particles from the silicide are included into portions of the stressed dielectric layer 116 in the vicinity of the gate electrode 108. Thus, a silicide corona 117, wherein the material of the stressed dielectric layer 116 comprises material sputtered from the silicide in portions 120, 121, 110, may be formed. The silicide corona 117 may increase the fringe capacity between the gate electrode 108 and electrical contacts formed for providing electrical connection to the source region 104 and the drain region 105, in particular in N-channel transistors, wherein the stressed dielectric layer 116 is not removed. This may adversely affect the AC performance of N-channel transistors. Moreover, the degrading of the silicide may lead to a greater contact resistance between the silicide and contact vias contacting the source region 104 and the drain region 105, or even to a loss of the electrical contact to the source region 104 and/or the drain region 105.
In view of the situation described above, the present disclosure relates to techniques that allow an improvement of the quality of transistors that are formed by means of manufacturing techniques wherein features comprising silicon nitride are partially or completely removed by means of etch processes.